RISC-V LIGHT RV32I Basic instruction set soft core IP

This is a very simple to implement RISC-V RV32I Basic instruction set parametrised soft core IP with all the necessary IO's for a basic utilisation.

The ideea to create this softcore had come from principle that the ISA for this core is open source, this way if the core is destinated to create projects that will be monetized does not conflict with any proprietary license.

This is a LIGHT implementation of RISC-V RV32I Basic instruction set that is not developed for speed but is developed for size, this core uses ~900LUT from XILINX Artix-7 device working at ~125Mhz and ~ 1950LUT from LATTICE MarchXO3 working at ~35Mhz.

This come with some basic IO's like paralel IO, UART, SPI, TWI, LCD interface, LCD to HDMI serializer and a simple GFX accelerator ( paint horizontal and vertical lines and fill rectangles with desired colors with speed of the core bus frequency).

Inside the core repository is a test project to compile a simple application running on this core, also I add support for this core and all IO's on MULTIPLATFORM-CPP-SDK under ExampleRiscFive_FPGA directory.

The example application on MULTIPLATFORM-CPP-SDK is made for Digilent NEXIS Video board and read the PmodNAV board sensor data connected to JC and display it to the onboard OLED display and on a HDMI display on a 1440x900 resolution display.
With SW0 can be selected the data that will be displayed, select data from LSM9DS1 and data from LPS25HB.
There is no example application inside MULTIPLATFORM-CPP-SDK directory for the LATTICE board.

The repository of this core on XILINX platform ( Digilent NEXIS Video ) can be found here.
The repository of this core on LATTICE platform ( LATTICE MachXOLF Starter Kit ) can be found here.

All dependencies are placed on this repository: https://github.com