arduFPGA Design Composer to easily compose designs for arduFPGA boards

This project is intended to easily compose custom FPGA designs even by developers that does not know how to write a FPGA  design.

The IDE will use something like drag and drop modules on a sheet and connect them together in the easiest way.

The IDE is at beginning of development, but with time will become a fully functional multi platform FPGA Design Composer.

Is done using MinGW to be available on all platforms Linux, Windows and MacOS.

Here is a print screen of the development level at this day:

The initial reason for developing this IDE was to easily compose designs for arduFPGA boards using LATTICE iCE40UP5K FPGA and will be extended to Xilinx Artix FPGA's, but as soon as the IDE will be usable will be made open source under GPLv2 license, will be open for everybody to contribute and edit the code to suit their needs.

Update:

At current stage adruFPGA Design Composer begin to generate some code.

arduFPGA-game-console runs arduino made games for arduboy, with dedicated audio codec

The board is designed around a LATTICE iCE40UP5K that implement a ATmega32U4 with the necessary IO's to run unmodified arduboy games, also ( optionally ) includes a VS1053b audio decoder to play music from uSD or create games with more complex sounds.

This board is a derivation of ARDUFPGA ICE40UP5K V1.1 board

https://digitalelectronicsandprograming.blogspot.com/2020/05/ardufpga-ice40up5k.html

in portable format with a size of only 68x43mm, smaller than a credit card.

As hardware, there is:

1x LATTICE iCE40UP5K.

1x SSD1306 OLED 128x64 BW display/ ST 7735S 160x80 color TFT display.

1x 2MB of SPI FLASH for the design, the GUI boot-loader and the user application (game), with an endurance of minimum 100K erase/write.

1x Optionally VS1053b dedicated audio decoder.

1x Electret buzzer.

1x RGB powerfull LED that can be used as flashlight without exiting the played games.

1x Dedicated battery charger with status LED's.

Design and firmware's:

Games and applications are load from a uSD card thru two stage boot-loader:

The first stage that is written inside the design and has its own 2KBytes of ROM memory and 512Bytes of RAM memory, it has even a dedicated interrupt vector named NMI that interrupt the running game every 1mS and check for INT button to be pressed, this is the service function that check if the INT button is press, if INT button is press between 100mS and 500mS this function will load the GUI boot-loader, if is press more than 500 mS will disconnect the keyboard from the running application and run the alternate functions.

Second stage is a GUI explorer/boot-loader that is loaded into the emulated ATmega32U4 program memory running like a normal application or a game and has integrated the FAT FS library, check and update the design and GUI boot-loader every time a game or application is launch, in case if the running design is custom made for that application or game, when the game or running application is interrupted the GUI boot-loader will automatically save the EEPROM content to the uSD card, and load the EEPROM content from uSD card when a game or application is started, so, all game scores and history is saved if the game is changed.

At this moment all games are in binary format, need to be converted from hex to bin files in order to run.

The design has the capability to increase the size of ROM and RAM memory according to each developer necessities, but no more than 128KB combined.

Different designs, applications source code,boot-loaders source code, user guides, schematic's and other stuff will be available on: https://github.com/dev-board-tech

Of course, design and application ideas are very welcome.

Update:

If you short press the INT button ( between 100mS and 500mS ) the game is interrupted and the EEPROM content is saved to the uSD memory.

If you press INT button more that 500 milliseconds, the keyboard is disconnected from the application, and buttons have other functionalities done by the first stage boot-loader that runs like a bios in background.

The features of the first stage boot-loader are: 

• INT+ B button change the LED colour B,G,R.
• INT+ A button turn ON/OFF the flashlight (RGB led becomes flashlight).
• INT+ UP increase the game volume in four steps, from mute to maximum.
• INT+ DN decrease the game volume in four steps, from maximum to mute.
• INT+ DN decrease the game volume in four steps, from maximum to mute.
• INT+ LEFT switch the USB connector function between UART RX/TX and video NTSC composite output.
• INT+ RIGHT switch the audio connector function between audio and video NTSC composite output, as protection to avoid driving the audio connector by VS10xx and the FPGA, when VS10xx is out of reset the audio connector can not be switch to composite output.

All this functionalities at the same tame when you playing games or listen music.

The volume mostly has effect on headphones, the electret buzzer does not react to much to the volume change, the volume is changed using two four bit PWN generators in the design that are connected to PORTA bit [3:2], bit [3:2] of the PWM are connected to '0' and bit [1:0] to PORTA, the real maximum volume is 1/4 of total power to avoid blowing up the listener ears :slight_smile: .

The audio connector is connected directly to VS1053b and three pins of the FPGA, this pins are used by the game as audio outputs but alternatively can be used as data communication, one of the pins needing to be put to '0' to provide the ground for the communication.

The USB type C connector is used for charging the battery, and for data communication, eight pins of the FPGA are wired to this connector, six of them are divided in three pairs of two wires that can be used for fast differential bidirectional communication and and are match between them or can be used as general purpose IO's, and two that can be used as general purpose IO's.

There is another 3 pin header named ONE-WIRE header.

BW version SSD1306:

Color version: ST 7735S:

The current design is a reduced IO, ATmega32u4 compatible core with 64KB of emulated FLASH memory and 32KB of RAM memory, TIM0, TIM3, TIM4, SPI, UART ( incomplete ), emulated EEPROM, extra-reduced PLL ( USB clock generator strip away ), 10bit LFSR RNG as ADC.

System IO's: 

* PIOA used for design FLASH chip select, application FLASH chip select. external chip select on the ARDVARK connector, and volume control as outputs, all seven keys and LoBat signal as inputs.

* Ports 0xDB-0xFF used for boot status and FLASH memory write registers.

The external chip select on the ARDVARK connector can be used as CS for an external SPI device connected to ARDVARK connector and in case if the user brick's the arduFPGA console to recover it using any other arduFPGA console or a regular SPI programmer.

Board consumption from the battery is 29mA with the display at maximum bright ~90% of the pixels active, uSD initialized, RGB LED OFF, and VS1053b in reset mode ( no consumption ).

The board is smaller than a credit card only 68x43x10mm in size and the space in the back of the board close to audio connector can be glued a battery up to 1Amp's in capacity giving a huge game play/ music listen time for one charge.

Here is a demo:

The board has pass the prototype stage, now I made the preparation to order the final board that will be available for purchase here: https://store.devboard.tech

arduFPGA iCE40UP5K a FPGA development board in arduino R3 board format

A new FPGA development board in Arduino R3 format is in development and will be available for purchase very soon, now the board is in final revision stage.

The board will be Open Source Hardware and will come with plenty of example designs around ATmega/Xmega and RISCv soft cores with the default PIO, UART, TWI, TIMER's, SPI and other peripherals that are found in an ATmega uC, all RTL source code is licensed under GPLv2.

Some of the designs can be used for day to day work, like Oscilloscope up to about 100M samples/second and logic analyzers.

The user guide can be download from http://download.devboard.tech/arduFPGA_iCE40UP5K_V1.1/arduFPGA_iCE40UP5K_user-guide.pdf

Will be available for purchase from https://store.devboard.tech/development-boards/1-5-ardufpga-ice40up5k-v10.html

The repository for all designs and source code can be found on https://devboard.tech/git

The board can be bought from https://store.devboard.tech

We have a delay of several days in in shipping the board due to COVID19

RISC-V LIGHT RV32I Basic instruction set soft core IP

This is a very simple to implement RISC-V RV32I Basic instruction set parametrised soft core IP with all the necessary IO's for a basic utilisation.

The ideea to create this softcore had come from principle that the ISA for this core is open source, this way if the core is destinated to create projects that will be monetized does not conflict with any proprietary license.

This is a LIGHT implementation of RISC-V RV32I Basic instruction set that is not developed for speed but is developed for size, this core uses ~900LUT from XILINX Artix-7 device working at ~125Mhz and ~ 1950LUT from LATTICE MarchXO3 working at ~35Mhz.

This come with some basic IO's like paralel IO, UART, SPI, TWI, LCD interface, LCD to HDMI serializer and a simple GFX accelerator ( paint horizontal and vertical lines and fill rectangles with desired colors with speed of the core bus frequency).

Inside the core repository is a test project to compile a simple application running on this core, also I add support for this core and all IO's on MULTIPLATFORM-CPP-SDK under ExampleRiscFive_FPGA directory.

The example application on MULTIPLATFORM-CPP-SDK is made for Digilent NEXIS Video board and read the PmodNAV board sensor data connected to JC and display it to the onboard OLED display and on a HDMI display on a 1440x900 resolution display.
With SW0 can be selected the data that will be displayed, select data from LSM9DS1 and data from LPS25HB.
There is no example application inside MULTIPLATFORM-CPP-SDK directory for the LATTICE board.

The repository of this core on XILINX platform ( Digilent NEXIS Video ) can be found here.
The repository of this core on LATTICE platform ( LATTICE MachXOLF Starter Kit ) can be found here.

All dependencies are placed on this repository: https://github.com

ATMEGA/ATXMEGA softcore IP

This is a very simple to implement MEGA/XMEGA parametrised soft core IP with all the necessary IO's for a basic utilisation.

Now that the FPGA's are on an affordable price, in some cases cheaper than an bare metal microcontroller ( for example LATTICE ICE40 UltraPlus ) and in some cases an equivalent soft core of an bare metal core is faster than the bare metal core, I developed a MEGA/XMEGA parametrised soft core with additional IO IP's like PIO, UART, SPI, TWI, LCD, GFX accelerator, even an LCD to HDMI translator for boards that have HDMI output connector on them.

The repository of this core on XILINX and LATTICE platform can be downloaded from here.

Intel HEX file to Verilog MEM file

This application is made to convert from Intel HEX format or BIN file to Verilog memory file format and is intended to be call by the compiler after HEX or BIN file was generated.

Below is an example of usage for Atmel Studio on Post build command line:

IntelHexToVerilogMem.exe -i "$(OutputFileName).hex" -o "C:\GitHub\XMEGA-CORE-IP-TST\core1ROM.mem" -g "2" -b "0x20000000" -s "2"

Below is an example of usage for Eclipse on Post build command line:

"${PWD}/IntelHexToVerilogMem.exe" -i "${PWD}\TestRiscVXilinx.hex" -o "C:\GitHub\VERILOG-RISC-V-LIGHT-CORE-IP-TST-XILINX\core1ROM.mem" -g "4" -b "0x8000" -s "2"

The -g argument is optional (default is 2) and indicate the length in bytes on a row, values supported are power of 2.

The -b argument is the offset of the memory, for example if the ROM memory start from 0x20000000 the addresses from 0 to 0x1fffffff is not included in output file.

The -s argument is optional and default value is 1, valid values are 1,2 and 4.

The -s argument is the split value, for example if -g = 4 and -s = 2 this application will output 3 files, one with 4 bytes on the row and two files with half a row each, file "core1ROM_0.mem" will contain bytes 1 and 0 from the 4 byte row and file "core1ROM_1.mem" will contain bytes 3 and 2 from the 4 bytes row.

If -s argument is four will output five files, one with four bytes on each row and five files each with one byte on each row from a four byte row, this will help to read memory's with byte level misalignment in one single clock cycle.

This argument is useful if you want to easily implement unaligned memory read and write in a single clock cycle.

For example for memory's with 32 bit per words if you want to read unaligned 32 bit data you can read the low 16 bit data from file "core1ROM_1.mem" and the high 16 bit data from address + 1 from file "core1ROM_0.mem".

Download application.

Raw file to C GCC array converter.

This application converts all files (txt, jpg, bmp, and other) to an constant array hat can be imported to any GCC compiler.
This application export a header fine and a source fine with ".h" and ".c" extension with the same name like imported file.
The input can be multiple files with no filter to extension.

From here you can download the application.

Lepton FLIR thermal image sensor PC application.

I made this application to display the Lepton FLIR thermal image sensor.

This application handle raw received data using uart interface.
The user send the image captured by image sensor in raw mode 80 * 60 * 2bytes = 9600 bytes with a pause of about 60 miliseconds.

This application can be downloaded from here. (this application requires .NET Framework 2.0)
From here you can download a SDK that include even the STM32-E407 board application example to work with Lepton FLIR thermal image sensor.
    From here you can get a simple driver to read data from image sensor using SPI interface.

The sensor will be connected as fallow:
Sensor CS -> PG10
Sensor CLK -> PB10/SPI2_SCK
Sensor MISO - > PC2/SPI2_MISO

BeagleBone Black bridge from USB0 device to eMMC and uSD.

On internet, even on TI forum the people asks how to access (read, write, modify & restore ) data from eMMC on BeagleBone Black.
I create two applications that can run from uSD, this applications bridge the USB device MSC to one of two interfaces MMCSD0 (uSD) or MMCSD1 (onboard eMMC).

The application which  bridge the USB0 to uSD will help the developers to modify the app files from uSD without pulling the uSD from BBB.

This two applications has not a fast data transfer but help the developers to restore read modify data on this two interfaces.

From here you can download the MLO (second stage bootloader) for BeagleBone and BeagleBone Black.
From here you can download the application that bridge USB0 to MMCSD0 (uSD) about 4MB/ read and from 130 to 400KB/s write depending to the uSD card, this application works on BeagleBone and BeagleBone Black.
From here you can download the application that bridge USB0 to MMCSD1 (eMMC) about 10-11MB/s read and 700KB/s write, this application works on BeagleBone if you connect a eMMC or a SD/uSD/MMC card on a expansion board on MMCSD1 pins, the eMMC can work in 1-4 or 8 bit data bus, but if you use the code on BeagleBone without connect a eMMC circuitry the application don't hangup.

For people that want to restore BBB original firmware, from here can download the image of eMMC.

Entire project can be cloned from here.

Audio Spectrum Analyzer V5 32x16 Truecolor Matrix Display

This Audio spectrum analyzer is a 32 frequency band with 16 levels each band, is a high quality real time FFT product, is a V5 class product and at this moment is in development.
Will be capable to process real time FFT audio signal and display the frequencies in different way, from a simple spectrum analysis displaying 32 frequencies with 16 levels each, to visual effects like plasma with full color ( minimum 4096 colors ).

MLO boot loader for BeagleBone and BeagleBone Black

This bootloader was compiled for both BeagleBone and BeagleBone Black, the bootloader read the EEPROM data to distinguish if run on BB or BBB.

This can be download from here

Fast Bootloader for BragleBone and AM335x

I made a third level bootloader, that can load user standalone applications more quickly than StarterWare bootloader.
Can be adapted to work with all boards with AM335x TI microcontroller.
The bootloader can load applications with approximately 4.5MB/s depending to the size of fat cluster, the speed of uSD memory card (if a cluster of uSD filesystem is 16KB the speed is higher than one uSD card with 8KB cluster).
This bootloader is made to be loaded at address 0x87F80000(at end of beaglebone RAM memory), If you want to load this bootloader on another location please don't hesitate to write me.
Your application will be named APP.BIN to be loaded by this bootloader.

From here you can download the bootloader.
From here you can download the TI SDCard boot utility.

AM335x SDK modified from StarterWare

After I bought a BeagleBone rev A6 boart and BeagleboneExpansion V2 CAP with a 800x480 display with capacitive touchscreen, I started to work with StarterWare available from TI.

On this SDK I try to create API's that will be very simple to use, like C#.

I try to arrange the drivers and API's and I added and translated some open source libraries.
The first result is a mix from AM335X_StarterWare_02_00_00_06 and AM335X_StarterWare_02_00_00_07.

On every version I will include a project that will show you how to use the SDK.

This SDK include the next files:

• API's

1. Delay API.
2. Gfx API.
3. GPIO API.
4. Interrupt API.
5. LWIP API.
6. MMCSD API.
7. MMU API.
8. PMIC API.
9. RTC API.
10. Capacitive touchscreen API(can read all five points).
11. Resistive touchscreen API.
12. TWI API.
13. Uart API.
14. USB API.
15. USB mouse host API.
16. USB MSC API.

•  Applications

1. Simple HTTP application(is a demo, respond only to "GET" command).

•  Devices

1. 24C TWI device driver.
2. ADXL345 device driver.

• Library

1. Bitmap decode library.
2. PNG decode library.
3. Jpeg decode library.
4. MPEG1/2 decode library.
5. Button library.
6. Check Box library.
7. Virtual Keyboard library.
8. List Box library.
9. Picture Box library.
10. Progress Bar library.
11. Scroll Bar library.
12. Text Box library.

• System

1. Cache.
2. Dmtimer.
3. Core Iit.
4. CP15.
5. Pin mux adc.
6. Pin mux LCD.
7. Pin mux MII.
8. Pin mux MMCSD.
9. Pin mux SPI.
10. Pin mux TWI.
11. Pin mux Uart.
12. Sys timer(you can create infinite timers with precision approximate to reference timer7).
13. Sys delay.
14. Watchdog.

This version has one issue:

When is loaded from bootloader the USB host can't be enabled (will freeze when the USB controller is setup), to set up the USB host is necessary to hardware reset or power up the board without uSD card inserted, after a watchdog reset has the same issue.
I already posted the issue on TI.

Download source code and bin files from here.

Download SD card format utility from here.

Load the app and MLO file with SD boot card utility from archive, after this copy the APP.BIN file to uSD card.

Xmega A1 Media Player development board

Features of this development board:

1. Main controller ATxmega64A1/ATxmega128A1/ATxmega64A1u/ATxmega128A1u.
2. On-board External 512KB SRAM memory ( AS6C4008 ).
3. One or two onboard 24c EEPROM ICS up to 2Mb, or 23K serial RAM memory, or combined.
4. One or two onboard uSD memory card sockets, with led to indicate activity of each uSD memory card.
5. On-board usart to USB converter ( FT232RQ), with RX/TX activity led.
6. On-board dedicated battery charger controller via USB connector ( MCP73871 ).
7. On-board dedicated resistive touch screen controller ( AR1020 ).
8. On-board dedicated RTC/64Bytes SRAM/128Bytes EEPROM circuit with backup high capacity capacitor ( MCP79410 ).
9. On-board Ogg Vorbis/MP3/AAC/WMA/MIDI codec ( VS1053b ) with jack 3.5mm audio output ,3 pin connector audio input and connector for button style Microphone, with led activity monitor on xDCS, xCS and and DREQ pins.
10. 320x240 TFT high quality display 8Bit bus mode ( MI0283QT-2 ) connected to external SRAM bus to increase speed of transaction using DMA working with him like a external SRAM.
11. One 30 pin extension peripheral connector with bidirectional 8bit data bus, unidirectional 8Bit A0-A7 address bus,7 chip select signals, RW and RD signals and one IRQ line.
12. On-board bus extension decoder to allow up to seven external peripherals directly accessed via external RAM bus ( 74LV138 ) and up to 256*7 external peripherals with external addresses decoders.
13. One lateral push button user defined(like PWR/Back).
14. One lateral push button reset function.
15. PDI programing connector.
16. JTAG debugging connector.
17. 3V VLDO power regulator for all circuits, to power this board from LI-IO battery on entire range of voltage ( 3.2 to 4.2V and 5V from USB connector).
18. 1.8V VLDO power regulator to power digital section on VS1053b circuit.
19. On-board NOKIA or HUAVEI battery connector.
20. Three pin connector to connect an external battery.
21. 29 IO pins accessed via two lateral 26 pin connectors ( entire B and C port, pin port A2-A7 and D1-D7 ).
22. Resistive divider to monitor the battery voltage.

 Down I posted several photos of board generated by a 3D software:

 In future for this board will be developed extra peripherals like:

• ATA high capacity hard disk shield.
• Secondary displays shield.
• Ethernet interface shield.
• Nand flash memory shield.
• Video sensor shield.
• Magnetometer shield.
• Gyroscope shield.
• Dedicated ADC shield to make oscilloscope.
• Video out encoder shield.
• Wireless communication shield.
• GSM communication shield.
• IR communication shield.
• Bluetooth communication shield.
• GPS shield.
• Motor stepper shield.
• Xbee shield.

And others.

This board will be delivered with a demo MP3 player project source code and a framework with library's and drivers special developed for this board.

How to setup avr studio 5 and 6 to use static library

I search entire internet for a explanation of error "undefined reference to" functions inside static library, but no explicit solution found.

For users that he cannot resolve this issue I will post two photos, how to set up the project to import functions from static libraries.

In this case the .h files is inside the "Directories" (photo2) and the .a files inside the "Debug" folder of each static library project(how is shown on bottom of first photo).

When you compile a static library the compiler generates a file named "libProjectName.a" on "Debug" folder, on top of first photo is shown how can be included the .a libraries, to include .a libraries is necessary to write the .a file name without "lib" and without ".a"inside a quote ("").
With this setup you can include and use static library.

Say NO to ACTA

Stereo digital audio spectrum analyzer V4.0

This is a stereo upgrade of previous version 3.x.

This version has multiple changes from the previous version, like:

V 4.0A is a version with 18 Bands + Two VU meters for right and left channels.

1. Can handle stereo signals.
2. Display format is 18+1+1( to display 18 bands of frequencies and Left Right signal level) .
3. USB adapter for easy upgrade.
4. Dedicated RTC with battery back-up.
5. Added two usart connectors to create cascade spectrum analyzers( to create large display from boards like this ).
6. A microcontroller twice faster that previous and multiple hardware advantages that increase speed of signal processing and display rendering.

Down I posted two photos with new board design.

 

 

V 4.0B is a version with 20Bands.

A 3D presentation of Audio Spectrum Analyzer 4.0B: