Saturday, March 17, 2018

Intel HEX file to Verilog MEM file

This application is made to convert from Intel HEX format or BIN file to Verilog memory file format and is intended to be call by the compiler after HEX or BIN file was generated.

Below is an example of usage for Atmel Studio on Post build command line:

IntelHexToVerilogMem.exe -i "$(OutputFileName).hex" -o "C:\GitHub\XMEGA-CORE-IP-TST\core1ROM.mem" -g "2" -b "0x20000000" -s "2"

Below is an example of usage for Eclipse on Post build command line:

"${PWD}/IntelHexToVerilogMem.exe" -i "${PWD}\TestRiscVXilinx.hex" -o "C:\GitHub\VERILOG-RISC-V-LIGHT-CORE-IP-TST-XILINX\core1ROM.mem" -g "4" -b "0x8000" -s "2"

The -g argument is optional (default is 2) and indicate the length in bytes on a row, values supported are power of 2.

The -b argument is the offset of the memory, for example if the ROM memory start from 0x20000000 the addresses from 0 to 0x1fffffff is not included in output file.

The -s argument is optional and default value is 1, valid values are 1,2 and 4.

The -s argument is the split value, for example if -g = 4 and -s = 2 this application will output 3 files, one with 4 bytes on the row and two files with half a row each, file "core1ROM_0.mem" will contain bytes 1 and 0 from the 4 byte row and file "core1ROM_1.mem" will contain bytes 3 and 2 from the 4 bytes row.

If -s argument is four will output five files, one with four bytes on each row and five files each with one byte on each row from a four byte row, this will help to read memory's with byte level misalignment in one single clock cycle.

This argument is useful if you want to easily implement unaligned memory read and write in a single clock cycle.

For example for memory's with 32 bit per words if you want to read unaligned 32 bit data you can read the low 16 bit data from file "core1ROM_1.mem" and the high 16 bit data from address + 1 from file "core1ROM_0.mem".

Download application.

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